An integrated circuit can be damaged when subjected to a voltage that is higher than the design voltage of the integrated circuit. Electrostatic discharge (“ESD”) originating from a source external to the integrated circuit can generate a voltage that is many times greater than the design voltage of the integrated circuit. Therefore, many integrated circuits incorporate ESD protection circuitry to prevent damage that may result from a voltage exceeding the normal operating voltage.
One mechanism that can cause circuit failures during ESD events is a phenomenon known as “bipolar snapback,” wherein an excessive voltage causes a parasitic bipolar transistor inside a MOS device to turn on causing the current consumed by the MOS device to rapidly multiply and potentially resulting in irreversible damage to the MOS device. Usually, the parasitic bipolar transistor inherently contained in the N-channel MOS device of, for example, an output buffer, is the most susceptible to snapback and is frequently the point of failure in a circuit subjected to an ESD event. In some implementations, an N-channel double reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device includes first parasitic NPN bipolar transistor between the N-type drain region and N-type source region (the lateral parasitic bipolar device) and a second parasitic NPN bipolar transistor between an N-type buried layer and the N-type source region (the vertical parasitic bipolar device).
During normal operation, the rated drain-to-source voltage of the LDMOS device is constrained by the breakdown voltage of the device, that is, the drain-to-source voltage is maintained at or below the drain-to-source voltage that causes avalanche breakdown in the LDMOS device. If the drain-to-source voltage of the LDMOS device exceeds the breakdown voltage during an ESD event, the LDMOS device remains operable and will continue to function normally provided the drain-to-source voltage decreases to a level below the breakdown voltage. However, if the drain-to-source voltage exceeds the snapback voltage during an ESD event, that is, the drain-to-source voltage that causes either and/or both of the parasitic bipolar transistors to turn on, the current consumed by the LDMOS device rapidly multiplies. Accordingly, to avoid interfering with normal operation, the ESD protection circuitry for an LDMOS device is typically designed to respond to a drain-to-source voltage greater than the rated voltage but less than the snapback voltage. However, efforts to minimize the on-resistance of the LDMOS device will limit the margin (i.e., the voltage difference) between the rated drain-to-source voltage and the actual breakdown voltage. Consequently, the margin between the rated source-to-drain voltage and the snap-back voltage will also be limited as the snap-back voltage is typically close to the break-down voltage, resulting in a narrow design window and more stringent manufacturing requirements for the ESD protection circuitry.